1. Field of Invention
The present invention relates to a driving circuit of a plasma display panel (PDP), and particularly to a reset circuit of a PDP.
2. Description of the Related Art
When driving a Plasma Display Panel (PDP), a cycle of a sequential reset period, addressing period and sustaining period is repeated for driving operations. Wherein, the operation during the reset period is used for clearing and resetting wall charges of PDP display cells; the operation during the addressing period is used for addressing the display cells; the operation during the sustaining period is used for sustaining luminance of the addressed display cells.
FIG. 1 is a schematic drawing of a conventional PDP driving circuit. For simplicity, only one display cell 103 and the driving circuit thereof are shown in FIG. 1, and the circuit for the operation during the addressing period is omitted. The display cell 103 has three electrodes, i.e. a scan electrode, a bulk electrode and an addressing electrode. In FIG. 1, a sustaining circuit 101 and a reset circuit 102 are electrically connected to the scan end of the display cell 103, while the sustaining circuit 104 is electrically connected to the bulk end of the display cell 103. The sustaining circuits 101 and 104 are symmetrical.
The sustaining circuits 101 and 104 serve for providing the display cell 103 with AC sustaining voltage during the sustaining period. The reset circuit 102 serves for producing a reset signal to the display cell 103 during the reset period, wherein the reset signal is used for clearing and resetting wall charges. Cp represents an equivalent capacitance of the PDP in the display cell 103. As a switch Q1 is on, the current from a voltage source Vd would pass through a diode D1 and the switch Q1, which results in a RC resonance of a resistor R and the capacitance Cp, further producing a reset signal for clearing and resetting wall charges. In this embodiment, the reset signal is an exponential waveform. The detail for controlling switches Q1˜Q7 during driving the display cell 103 should be known to those skilled in the art and are not repeated herein.
The disadvantage of the above-described conventional scheme is when the wall charges are to be effectively cleared and reset, a feeble discharge is essentially needed, making the voltage applied to the capacitor Cp slowly fall. The slowly falling of the voltage requires a longer reset time, but the longer the reset period, the longer the backlight is up. Thus, the sustaining period affecting the average luminance of a display cell would be accordingly shorter and the display quality degrades. On the other hand, the equipped resistor R requires a more complex process and a higher cost.
Although the sustaining circuit 101 may provide an LC resonance between an inductor Ls and a capacitor Cp, the resonance frequency and reset waveform required by each is different. The resonance of the sustaining circuit 101 actually plays a much different role from the resonance to build up the reset signal, limiting and confining the application of the resonance of the sustaining circuit 101.